Advanced Customisation: MGT Speed

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This page describes in more detail the link speed assignation and its connection to the clock. Following from Walkthrough1: creating your own repository from scratch this extends Step 5 with:

Step 5b: Set-up the EMP project declaration file

As described in Step 5: Create the emp_project_decl package you need to create a VHDL package, named emp_project_decl, that defines several configurable settings of the EMP framework, such as clock frequencies for receiving data from the I/O channels, and which firmware components are instantiated in each datapath region (e.g. input buffers, output buffers, input transceiver control logic, output transceiver control logic).

If you have not integrated custom payloads into the EMP framework before, it is easiest to start from the emp_project_decl package for one of the example designs; copy the appropriate file from the table below to the src/my-algo-repo/an-algo/firmware/hdl/ directory, renaming the file to emp_project_decl.vhd (or another name if preferred).

In Step 5: Create the emp_project_decl package the reference files were set with clock ratios for specific MGT speeds. This meant the SM1 and SO1 designs have link speeds set to 16G for the GTH transcievers and 25G for the GTY transcievers. Below are alternate files which have the clock ratios set for 16G link speeds.

Board

Dependency file command

Serenity KU15P SM1

src/emp-fwk/projects/examples/serenity/dc_ku15p/firmware/hdl/sm1/emp_project_decl_240MHz.vhd

Serenity KU15P SO1

src/emp-fwk/projects/examples/serenity/dc_ku15p/firmware/hdl/so1/emp_project_decl_240MHz.vhd

These have the CLOCK_RATIO set to 6 for all MGTs as opposed to a mixture in the standard case. Before the data IO clock and 1st aux clock is configured at 360 MHz (clock ratio = 9). IO clock and Algo (aux) clocks can be set independently provided that they are both multiple of clock common ratio. For running at 16G link speeds, a 240 MHz clock is required which means the CLOCK_RATIO needs to be 6 as well as setting the CLOCK_RATIO_AUX to 2,4 and 6. This will give aux clocks at 240 MHz, 160 MHz and 80 MHz. Alternate ratios can be chosen as requireed.

  • NB: All cross chip regions shold be set to gty16 from gty25.