Reference bitfiles

The results from automated (GitLab CI) builds of the ‘null algo’ example designs for the latest tag can be downloaded from the following URLs:

• Dev boards:

  • HiTech Global K800

  • MPUltra

  • Xilinx VCU118

• Apollo:

  • Apollo CMv1 VU7P

  • Apollo CMv2 VU13P

  • Apollo CMv2 VU13P

  • Apollo CMv2 VU13P

  • Apollo CMv2 VU13P

  • Apollo CMv2 VU13P

  • Apollo CMv2 VU13P

  • Apollo CMv2 VU13P

  • Apollo CMv2 VU13P

• Serenity S1:

  • VU9P-2 (CSP in 2 regions)

  • VU9P-2 (CSP in 2/3 of regions)

  • VU9P-2 (CSP in all regions)

  • VU13P-1 (CSP in 2 regions)

  • VU13P-2 (CSP in 2 regions)

  • VU13P-2 (CSP in 2/3 of regions)

  • VU13P-2 (CSP in all regions)

• Serenity Z1 daughter cards:

  • KU115 BM1/TM1

  • KU115 SO1

  • KU15P SM1 v1 (360MHz payload clock)

  • KU15P SM1 v1 (240MHz payload clock)

  • KU15P SM1 v1 (GBT build)

  • KU15P SM1 v1 (lpGBT build)

  • KU15P SM1 v2 (360MHz payload clock)

  • KU15P SM1 v2 (240MHz payload clock)

  • KU15P SO1 v1 (360MHz payload clock)

  • KU15P SO1 v1 (240MHz payload clock)

  • KU15P SO1 v1 (lpGBT build)

  • KU15P SO2 v0 (360MHz payload clock)

  • KU15P SO2 v0 (240MHz payload clock)

  • KU15P SO2 v0 (lpGBT build)

  • VU7P SO1 v1.0

  • VU7P SO1 v1.1

  • VU7P SO1 v1.1 (lpGBT build)

  • VU9P SO1 v1.1

  • VU9P FO2

  • VU9P SO2

  • VU13P FO2

  • VU13P SO2 (360MHz payload clock)

  • VU13P SO2 (360MHz payload clock, Rx CSP only)

  • VU13P SO2 (360MHz payload clock, Tx CSP only)

  • VU13P SO2 (240MHz payload clock)

  • VU13P SO2 (lpGBT build)

The tarball downloaded from each of the above links contains the bitfile (top.bit) and all of the address tables required to communicate with the firmware (stored in the addrtab directory, top-level file addrtab/top_emp.xml).