Serenity Artix firmware: Release notes

Version 0.3.2

Created on 30th August 2020.

  • Fixed bug in I2C masters, which led to no acknowledge received errors when communicating with Firefly modules (and could only be resolved by reboot when using previous firmware versions).

Version 0.3.1

Created on 27th April 2020.

  • TTC: Updated control bus interface to allow for indepdendent selection of clock and data sources (internal vs external)

    • Corresponding change from v0.2.2 was accidentally reverted in v0.3.0

Version 0.3.0

Created on 8th April 2020.

  • Updated JTAG master to speed up programming

  • Added SPI master

Version 0.2.2

Created on 18th March 2020.

  • TTC: Updated control bus interface to allow for indepdendent selection of clock and data sources (internal vs external)

  • Removed local implementation of IPbus-over-PCIe interface - replaced by standard IPbus-over-PCIe interface from ipbus-firmware repository.

  • Updated project settings file to build with version 0.5.2 of IPBB

Version 0.2.1

Created on 23rd August 2019.

  • Duplicated TTC clock onto LVDS 4 as fix for KU15P SM1 v1 daugther cards (i.e. TTC clock is now sent onto LVDS 3 and 4)

Version 0.2.0

Created on 18th August 2019.