Artix TTC¶
The TTC firmware for the Artix-7 FPGA on the Serenity can receive a legacy TTC signal from the backplane and retransmit the LHC clock and TTC commands to each of the daughter card sites via LVDS. It can also be used to locally generate a 40MHz clock and TTC commands, allowing for synchronised data transfer between the North and South daughter cards without any external clock/TTC source.
The TTC logic is controlled and monitored using the serenitybutler
script
(in particular, the artix
subcommands).
Note
Before running the commands in the sections below, you need to create a Serenity butler config file (YAML format) that defines which address table should be used for the Artix.
The address tables for the latest Artix firmware are
installed by the SMASH RPMs under /opt/smash/etc/serenity/base/uHAL/v0.3/
,
with the top-file named top_artix.xml
. The Artix address table is
specified by the artix
field in the Serenity butler config file’s
address
map, and so a minimal config file - sufficient for all of the
commands in this page - is:
address:
artix: /opt/smash/etc/serenity/base/uHAL/v0.3/top_artix.xml
The location of this config file can be specified either through the -c
argument of serenitybutler
, or by setting the SERENITY_CONFIG
environment variable - e.g:
export SERENITY_CONFIG=/path/to/serenity.xml
Configuring the TTC firmware¶
The TTC logic can be reset and configured to distribute the clock/TTC signals received from the backplane (i.e. use the external TTC source) by running the following command:
serenitybutler artix reset external
Or, the TTC logic can be reset and configured to distribute internally-generated clock/TTC signals as follows:
serenitybutler artix reset internal
Checking the firmware version¶
In case you’re unsure which version of the Artix firmware is loaded, you can check this by running:
serenitybutler artix info