Release notes¶

Version 0.6.1¶

Created on 23th January 2022.

Serenity Z1.2: Add clock and crosspoint switch configs required to use the TCDS2 links to/from the DTH
PCIe udev rules: Use sysfs rather than dmesg

Version 0.6.0¶

Created on 14th November 2021.

Backward-incompatible changes

Given that the software now supports Z1.2 and Z1.2, the existing Z1.1 bare board configs in /opt/smash/etc/serenity/configuration/ have been renamed as follows:
```
BareBoard.smash -> BareZ1p1.smash
BareBoard_a35.smash -> BareZ1p1_a35.smash
```

Main improvements:

LTMs: Added mechanism to disable the global/rail addressing (so that the LTMs can still be brought up/down as a group, but the 3v3 on Serenity 1.2 may be excluded)
Fireflys: Added support for setting pre-emphasis on > 20G parts, and de-emphasis on <20G parts
- Also reorganised implementation of Firefly component more widely.

Version 0.5.2¶

Created on

Add support for Serenity Z1.2
- Bare board config: /opt/smash/etc/serenity/configuration/BareZ1p2.smash
NDM: Fixed bugs in measurements (“I2C no acknowledge received” exceptions)
Firefly: Fix temperature measurement bug (alternating valid and unphyiscal values), limited transfer size to 4 bytes, and more generally adhere to TWI spec rather than I2C.

Version 0.5.1¶

Created on 26th June 2021.

Updated to uHAL v2.8
Switch to pybind11 for Python bindings

Version 0.5.0¶

Created on 24th March 2021.

Backward-incompatible changes

Updated Pluggable base class to issue warning if socket and plug names do not match. As a result, on Serenity v1.1:
- Daughter card components must be named DC0 or DC1
- Firefly modules must be named Jn:mm (with the values n and mm matching the corresponding site)

Minor improvements

Reorganised implementations of I2C page handling to avoid duplication across different components
Updated Makefiles and code to support clang-based builds
Fixed some errors in inline documentation
Assorted cleanup, including: moving some constants out of global scope; removing dependence of core library on uHAL

Version 0.4.0¶

Created on 28th January 2021.

Fixed bug in udev ‘remove’ rule
- Previously this rule was not run when a device was powered off, and so corresponding device file symlinks were not deleted.
Reorganised Firefly components
- Merged FireflyBi, FireflyRx and FireflyTx classes into single Firefly class
- Added support for newer parts
Updated method for connecting to multiple FPGAs in daisy chain
- For daisy chain: JTAGmux "Connect All Targets"
- For single target: JTAGmux "Connect Default Target"
Added measurements for Si5345 clock synthesisers
Updated documentation (auto-generated by new tooling)
Updated internals to use C++11 features and libraries

Version 0.3.8¶

Created on 28th January 2021.

Extended deprecation date for old Serenity Artix JTAG interface (used in v0.2.x of Artix FW) to 1st July 2021.

Version 0.3.7¶

Created on 18th September 2020.

Added FTDI and SEMA components.
Note

This involved adding the Artix FPGA to the base board config files, and as a result of this the following line will no longer work:
```
Run /opt/smash/etc/serenity/base/atca/*.smash
```
Instead, that should be replaced by one of the following config files:
- For almost all boards: Run /opt/smash/etc/serenity/configuration/BareBoard.smash
- For those with an A35 Artix (only the first few boards): Run /opt/smash/etc/serenity/configuration/BareBoard_a35.smash
Added config for Serenity VU7P daughter cards: serenity/DaughterCards/VU7P.smash
Shortened names of existing Serenity daughter card config files:
- Imperial_KU115.smash becomes KU115.smash
- KIT_KU15P.smash becomes KU15P.smash

Version 0.3.6¶

Created on 9th July 2020.

Extended deprecation date for old Serenity Artix JTAG interface to 1st October.

Version 0.3.5¶

Created on 13th June 2020.

Updated code & makefiles to add support for CentOS8
XilinxFPGA component: Added measurements for System Monitor (can be read via either I2C or JTAG)

Version 0.3.4¶

Created on 14th May 2020.

Added option to specify timeout for locking shared mutex
Fixed bug in shared mutex permissions, so that writeable for all users
Updated implementation of makefiles and packaging files

Version 0.3.3¶

Created on 9th April 2020.

Updated XilinxFPGA and ‘JTAG master’ code to support new JTAG master interface in v0.3.0 of Serenity Artix FW. Note: This release of SMASH still supports the previous JTAG master interface as well.

Version 0.3.2¶

Created on 23rd March 2020.

Console: Fix bug encountered in pasting (only 1 in 16 characters were read).

Version 0.3.1¶

Created on 19th March 2020.

Updated Serenity Artix address tables for v0.2.2 of Artix FW.

Version 0.3.0¶

Created on 7th March 2020.

Added protection against conflicts between multiple simultaneous SMASH sessions in different processes
Updated to uHAL version 2.7
Updated Smash class to no longer be a singleton
Fixed memory leaks in Smash and Element classes

Version 0.2.9¶

Created on 9th February 2020.

Updated XVC server and console to boost ASIO-based implementation using dedicated worker thread
Python: Added Element attributes method
Cleaned up makefiles

Version 0.2.8¶

Created on 9th February 2020.

Python: Added Element measurements method

Version 0.2.6¶

Created on 16th December 2019.

Added ability to directly reset the I2C master firmware block
Daughter card config files: Fixed I2C address for EEPROM
Fixed bug causing direct JTAG loading to fail on 2nd attempt in single SMASH session

Version 0.2.5¶

Created on 30th November 2019.

Added ability to reset I2C port expanders
Fixed FPGA speed and temperature grade in config file for Serenity KU15P daughter-card

Version 0.2.4¶

Created on 27th November 2019.

Added ability to directly program FPGAs (i.e. bypassing an XVC server)
Fixed temperature and speed grade fields in config file for Serenity KU115 daughter-card
Created Python bindings for core SMASH functions

Version 0.2.3¶

Created on 24th October 2019.

Renamed some of the example configuration files (TomOpticalTests.smash becomes OpticalTests.smash)
Added ‘PCIe utilities’ package: Includes new set of udev rules that created the /dev/serenity_pcie symlinks
Added Serenity butler (serenitybutler), to replace previous Artix butler (abutler) script

Version 0.2.2¶

Created on 7th October 2019.

Add missing file required for configuring the clock synthesisers.
Main executable: Add --quiet and --verbose flags.
Updated core and component classes to use same logging library.

Version 0.2.1¶

Created on 20th September 2019.

Firefly: Corrected units of optical power measurements (issue #17)
Firefly: Added LOS, LOL and Laser fault alarms as measurements (issue #18)
Firefly: Removed measurements for registers whose values don’t conform to specs (Part Number, Revision Number, Serial Number and Date Code) (issue #19)
LTM4677: Added status & fault log measurements, and functions for clearing those registers (merge request #33)

Version 0.2.0¶

Created on 20th August 2019.

Serenity: Added address tables for v0.2.0 of the Artix FW
Serenity: Updated base-board SMASH scripts to use address tables for v0.2.0 of Artix FW
FPGA element: New functions - PCIe reset, Unprogram and Reload - and new measurement - Config state
FPGA Validate function: Added checks on power configuration (i.e. voltage/current within Xilinx-specified ranges)

N.B. v0.2.x of the Artix FW should be loaded on boards before updating to this release

Version 0.1.4¶

Created on 13th July 2019.

Added Assert command
PMbus element: Fixed paging bug
Added DummyComponent class for test purposes
EEPROMs: Implemented read and write functionality

Version 0.1.3¶

Created on 11th July 2019.

Serenity PCIe disconnect script: Updated so that runs lspci multiple times in case of error

Version 0.1.2¶

Created on 8th July 2019.

Added abutler script for controlling Serenity Artix TTC FW
Improved Print command output for power-related elements

Version 0.1.1¶

Created on 25th June 2019.

XVC server: Fixed bug in host IP address resolution

Version 0.1.0¶

First tag; created 23rd June 2019.